Job ID: JR0085258
Job Description: In this role, the Senior Digital Physical IC Design Engineer will be part of the team contributing to Silicon Photonics Solution Group's mission to transform and lead datacenter connectivity and enable Intel's differentiation in the networking space. As a Senior Engineer, the individual will be involved in challenging projects and drive it to completion in record time. You will quickly ramp on the existing flow, understand the challenges, and produce the work plan. Your expertise in deep submicron technology, processor design, and teamwork skills will be highly leveraged to guide activity across the entire cross-discipline, multi-site team. You will work with others to identify the issues, get buy-in on proposed solutions, and implement the solutions in time for the team to execute to schedule.
Inside this Business Group
The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post-silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.
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Motivation to drive an exciting project.
Needs to be familiar with all aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning and hard IP integration.
Experience solving SoC issues such as ESD strategies, mixed-signal block integration, and package interactions
Familiar with the hierarchical design approach, top-down design, area budgeting, and physical verification convergence.
A detailed understanding of database management issues will be requiredExpertise using leading-edge EDA tools Synopsys, Cadence or Mentor Graphics From a CAD tool perspective, experience with floorplanning tools, P&R flows and physical design verification flows is required.
Familiar with various process-related design issues including Design for Yield and Manufacturability, multi-Vt strategies and thermal managementTCL and Bash mastery are a necessity Make, Perl and Python expertise is nice to have.
Ability to provide mentorship and guidance to junior engineers and be a very effective team player.
Experience in integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
Ability to plan, execute, course correct and optimize blocks and SoC level implementations.
Good Understanding of LPDDR/DDR JEDEC specifications and related DDR Protocols
Good understanding of design for yield and exposure to production challenges in latest technology process node
Cross-discipline knowledge in any of these areas, such as Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, Memory IO training MRC and HAS/MAS specification documentation.
Minimum of 10 years in VLSI Design with expertise in RTL-to-GDSII flow, floor planning, Clock tree synthesis and block-level/chip-level signoff.
Must have experience in integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
Experience in custom / data-path implementation is highly desirable.
BE/B.Tech/ME/M.Tech/MS in Electrical & Electronics Engineering
Strong written and oral communication skills.
Excellent verbal and written communication skills.