IO PHY Architect

Job ID: JR0086036
MIG Malaysia is seeking IO PHY Architects to join our talented and vibrant team. You will have the opportunity to directly involved in defining the next-generation of Memory IO or On-Package IO architecture for SOC application on Intel leading process node.

Inside this Business Group

The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.

Innovate and own Architecture, Design, and Development of high performance, low power IO PHY meeting latest Memory Industry Standards for LPDDR, DDR Or Proprietary On-Package Interconnects standards
Owns PHY level Architecture study and recommends design trade-off aligned to IP/SoC requirement and roadmap
Collaborate across functional teams - Logic, Circuit, Verification, Structural Design in PHY level definition meeting Best In Class Power, Performance and Area metrics
Collaborate with SoC integration teams on PHY level requirement and integration issues
Mentor and develop a technical leadership pipeline.

Good Understanding of LPDDR/DDR JEDEC specifications and related DDR Protocols
Good understanding of design for yield and exposure to production challenges in latest technology process node
Cross-discipline knowledge in any of these areas, such as Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, Memory IO training MRC and HAS/MAS specification documentation.

Experience in Circuit u-Architecture definition of High-Speed Memory Interfaces example DDR, LPDDR, GDDR, or On-Package Interconnect IO interfaces, Ultra-Low Power Die-to-Die IO, PCIe, Serdes. The design achieved production in high volume and extensive exposure on post-silicon debug and BIOS-based PHY training algorithm
Experience in high-speed custom building blocks for High-Speed Interfaces, RTL logic design, Synthesis, Physical design, Power analysis and/or integration aspects for IO PHY in SoC

BSEE with 15+ years of relevant experience or Master's with 10+ years of relevant experience required.

Strong written and oral communication skills